Integrated Circuit (IC) production process can be divided into two main stages. FEOL (Front-end of line) consists in a fabrication of active devices like transistors or diodes on a semiconductor substrate (typically silicon). BEOL (back-end of line) is the remaining part of IC fabrication process with a principal goal of creating the interconnections between the active devices. BEOL process generates a stack of subsequent metallization layers (typically Al, AlCu alloy or Cu) separated with IMD (inter-metal dielectric) (typically Silicon Dioxide) and vias which are small openings in the inter-metal dielectric that are filled with a conductor (for example Tungsten) in order to provide vertical connections from one metallization layer to another. In a typical IC technology vias have a fixed size optimized for minimum diameter providing reliable contact and wherever a lower via resistance is required a matrix of such vias is used. Furthermore in a technology with a plurality of metal and via layers, some via and metal layers deposited further from the substrate may have a higher thickness than those deposited closer to the substrate. Such an arrangement is typically used in order to provide lower global interconnection resistance or to build integrated inductors with improved quality factor. BEOL process is usually finished by a deposition of a passivation layer like Silicon Nitride that provides additional protection of an IC.
The paper of DAI, CHING-LIANG, et al.—“A maskless wet etching silicon dioxide post-CMOS process and its application” discloses a variety of micromechanical components monolithically integrated on a standard IC by means of freeing a part of the BEOL interconnection stack through IMD isotropic etching.
Such a technique, which is an example of BEOL micromachining, can provide a very cost-effective solution for the production of a variety of relatively small microelectromechanical elements like radio-frequency (RF) switches (for example US 20120280393 A1), filters or resonators. However so far, it has been less successful as a method of fabricating more bulky devices like accelerometers or gyroscopes.
Capacitive accelerometers or other inertial sensors require a relatively big mass and high sensing capacitance in order to translate an inertial movement to an electrical signal. For this reason they are usually made using a dedicated production process. Most of the attempts of using BEOL-micromachining for that purpose required several additional etching steps like reactive-ion-etching of the BEOL and/or substrate anisotropic or deep reactive-ion etching. These steps are disruptive for an IC production process and increase its cost. Also they impede micromechanical device integration on top of the integrated circuit.
The isotropic etching of IMD is a simple additional post-process consisting in insulator removal from a part of the integrated circuit interconnection stack, which results in obtaining hollow spaces between the interconnection layers, thereby some part of the interconnections form micromechanical structures. Such a process can be performed through wet or dry etching using any etchant that dissolves the inter-metal dielectric while is selective to the metallization and via layers. An example of an etchant that is used to remove silicon dioxide and is selective to aluminum is Silox Vapox III produced by Transene and used in DAI, CHING-LIANG, et al.—“A maskless wet etching silicon dioxide post-CMOS process and its application”. Other examples can be found for example in FERNANDEZ, DANIEL, et al. “Experiments on the release of CMOS-micromachined metal layers.” Journal of Sensors, 2010. If the etching is wet it is usually followed by critical-point drying process or by a rinse in a low surface tension liquid like isopropanol or methanol. These steps minimize stiction problems. The part of an IC that is a subject of etching can be selected by an opening in the passivation layer. Optionally a hard mask or photoresist can be used to protect the passivation.
The main difficulty in using the IMD isotropic etching to produce accelerometers, gyroscopes or other bulky micromechanical devices is the necessity of using several metallization layers in order to provide sufficiently big and thick mass and high sensing capacitance. The isotropic nature of the etching step leads however to a partial or total IMD removal from the space between the metallization layers depriving the micromechanical structures of the adhesive forces between the metal and IMD. In this case the remaining adhesive forces provided by standard vias may be insufficient to preserve micromechanical device integrity—the micromechanical device may get damaged due to residual stress, temperature change, mechanical shock or other phenomena.
US-A1-2013/299924 relates to a component system including at least one MEMS element, a cap for a micromechanical structure of the MEMS element, and at least one ASIC substrate. The micromechanical structure of the MEMS element is implemented in the functional layer of an SOI wafer. The MEMS element is mounted face down, with the structured functional layer on the ASIC substrate, and the cap is implemented in the substrate of the SOI wafer. The ASIC substrate includes a starting substrate provided with a layered structure on both sides. At least one circuit level is implemented in each case both in the MEMS-side layered structure and in the rear-side layered structure of the ASIC substrate. In the ASIC substrate, at least one ASIC through contact is implemented which electrically contacts at least one circuit level of the rear-side layered structure and/or at least one circuit level of the MEMS-side layered structure.
U.S. Pat. No. 5,618,752 discloses a surface mountable integrated circuit and a method of manufacture. A wafer has a die with an integrated circuit in one surface of the wafer. A via extends to the opposite surface. The via has a sidewall oxide and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong or a receptacle. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.
WO-A1-2005061376 discloses a method of enclosing a micromechnical element formed between a base Layer and one or more metallization layers. The method includes forming one or more encapsulating layers over the micromechanical element and providing an encapsulating wall surrounding the element extending between the base layer and the one or more encapsulating layers. An electrical connection is provided between the base layers, and the one or more metallisation layers formed above the micromechanical element.